Hardware Engineer
Job Description:
Responsible for the development and support of electronic board designs in network security appliances.
Responsible for the individual development tasks and proper specifications and documentation for printed circuit boards including layout and assembly; and that the board integrates well with the rest of the embedded system; including software and mechanicals.
Minimum Qualifications:
-BS in Electrical Engineering or equivalent
-Minimum of 2-3 years experience in developing complex, high speed, FPGA and ASIC based embedded networking systems
-Experience with common engineering design tools: Schematic Capture (ViewLogic or Mentor Graphics), SPICE, PCB layout
-Experience with Semiconductor ICs, Integrated Circuits, SOC, CPUs and high speed memories
-Experience with lab debugging and verification/characterization and strong troubleshooting skills for high speed digital systems
-Generation of functional specifications and other pertinent documentation for assembly, test, and diagnostic development
-Supported transition of boards designs into manufacturing environments
-ASIC or FPGA coding in Verilog and/or VHDL
-Xilinx or Altera FPGA design tools
-Writing test benches for ASICs or FPGA designs in HDL
-Running regression test suites based on test benches
-Integrating 3rd party IP cores into ASICs or FPGA designs
-Working knowledge with one or more Xilinx and Altera devices; specifically Sparten-3 series, Virtex-2 or later series, Cyclone-2 or later series, and/or Stratix-1 or later
-HDL synthesis with vendor tools or Synopsys or Simplicity
-Floor planning a design, particularly with respect to I/O banks that incorporate different I/O levels or technology (LVTTL, LVDS, SSTL)
-Place and route, especially incremental design changes
-Writing design documents that describe the operation of a module, design, or implementation including
analyzing state-machines associated with a design.
-Debugging FPGA designs using JTAG based analysis tools (e.g. Chipscope or SignalTap)
-Adding logic analyzer interfaces to an existing FPGA design
-SW programming capability in C/C++ is desirable
-Familiarity with communication protocols such as USB, Smart Card, PCI, SPI3, I2C, MicroWire, Ethernet, and XAUI is desirable
-Required to use test equipment such as oscilloscopes, logic analyzers, etc. in a lab environment
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